1. Technical Field
The present invention relates to a chip package including stacking semiconductor devices and a method for forming the same.
2. Background
A three-dimensional integrated circuit is built by stacking dies and interconnecting them vertically such that they can behave as a single device. The stacked dies can be interconnected using TSV (through silicon via) technology such that the three-dimensional integrated circuit can have a small footprint.
Normally, TSVs are extremely large; they are a few times larger than gates and memory cells. Furthermore, when TSVs are fabricated, tensile stresses occur around the TSVs, which may cause significant carrier mobility variation. A keep-out zone surrounding a TSV is introduced to prevent devices or cells from being influenced by the TSV-induced stresses.
A conventional three-dimensional integrated circuit has a chip select mechanism, which uses TSVs as a vertical connection. Usually, the TSVs are arranged along one direction. Due to the large sizes of the TSVs and the keep-out zones they create, the linearly arranged TSVs consume a large die area, resulting in a large die or limiting the number of dies to be stacked in the three-dimensional integrated circuit.